The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
A particular challenge, and one which has become increasingly difficult for reduced device geometries, relates to the substrate planarization requirements during device fabrication. Chemical mechanical polishing (CMP), a process that serves to remove substrate material and thus planarize a surface of the substrate, is a process that is used throughout the semiconductor industry to address such substrate planarization requirements. However, in various situations, a CMP process alone is inadequate, and in fact could be detrimental, to some semiconductor substrates that include a variety of semiconductor device types. For example, a semiconductor substrate may in some cases include both high-voltage transistors (HVTs) and low-voltage transistors (LVTs). In some cases, the HVTs may be formed within a high-voltage (HV) region of the substrate, and the LVTs may be formed within a low-voltage (LV) region of the same substrate. In at least some examples, the HVTs have a substantially thicker gate dielectric than the LVTs. As a result, a top gate stack surface of the HVTs and LVTs may not be co-planar with each other. Thus, in some cases, a metal gate CMP process that polishes down to a top surface of the shorter LVT gate stack may simultaneously over polish the HVT gate stack, thereby damaging the HVT gate stack.
Thus, existing processes have not proved entirely satisfactory in all respects.